CS8900-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8900-IQ Datasheet PDF : 138 Pages
| |||
CS8900A
Crystal LAN™ ISA Ethernet Controller
4.3.3 Interrupt Number
(Read/Write, Address: PacketPage base + 0022h)
Address 0023h
00h
Address 0022h
Interrupt number assignment:
0000 0000b= pin INTRQ0
0000 0001b= pin INTRQ1
0000 0010b= pin INTRQ2
0000 0011b= pin INTRQ3
0000 01XXb= All INTRQ pins high-impedance
The Interrupt Number Register defines the interrupt pin selected by the CS8900A. In a typical application the follow-
ing bus signals are tied to the following pins:
Bus signal
IRQ5
IRQ10
IRQ11
IRQ12
Typical pin connection
INTRQ3
INTRQ0
INTRQ1
INTRQ2
See Section 3.2 on page 17.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state, which corre-
sponds to placing all the INTRQ pins in a high-impedance state. If an EEPROM is found, then the register’s initial
value may be set by the EEPROM. See Section 3.3 on page 18.
Reset value is: XXXX XXXX XXXX X100
4.3.4 DMA Channel Number
(Read/Write, Address: PacketPage base + 0024h)
Address 0025h
00h
Address 0024h
DMA channel assignment:
0000 0000b= pin DMRQ0 and DMACK0
0000 0001b= pin DMRQ1 and DMACK1
0000 0010b= pin DMRQ2 and DMACK2
0000 0011b= All DMRQ pins high-impedance
The DMA Channel register defines the DMA pins selected by the CS8900A. In the typical application, the following
bus signals are tied to the following pins:
Bus signal
DRQ5
DACK5
DRQ6
DACK6
DRQ7
DACK7
Typical pin connection
DMRQ0
DMACK0
DMRQ1
DMACK1
DMRQ2
DMACK2
See Section 3.2 on page 17 and Section 5.4 on page 89.
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state which corre-
sponds to setting all DMRQ pins to high-impedance. If a EEPROM is found, then the register’s initial value may be
set by the EEPROM. See Section 3.3 on page 18.
Reset value is: XXXX XXXX XXXX XX11
CIRRUS LOGIC PRODUCT DATASHEET
42
DS271PP4
Share Link: 