
Detailed Specifications
4.4.3 Input data latch cycles for NAND Flash interface
Figure 7: Input data latch cycle
CLE
CE_n
ALE
WE_n
IO[0:7]
tALS
tWC
tWP
tWH
tDS tDH
DIN0
DIN1
tCLH
DIN511
4.4.4 Sequential output cycle after read for NAND Flash interface
Figure 8: Sequential output cycle after read
CE_n
RE_n
IO[0:7]
RB_n
tRC
tRP
tREH
tREA
tRR
Dout
Dout
Dout
STV0674
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