STTS2002(2011) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STTS2002
(Rev.:2011)

2.3 V memory module temperature sensor with a 2 Kb SPD EEPROM

STMicroelectronics 

Temperature sensor registers

STTS2002

Table 9. Configuration register bit definitions

Bit

Definition

Event mode

0 – 0 = Comparator output mode (this is the default).

– 1 = Interrupt mode; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it is

unlocked.

Event polarity(1)

The event polarity bit controls the active state of the EVENT pin. The EVENT pin is driven to this state

when it is asserted.

1 – 0 = Active-low (this is the default). Requires a pull-up resistor to set the inactive state of the open-

drain output. The power to the pull-up resistor should not be greater than VDD + 0.2 V. Active state

is logical “0”.

– 1 = Active-high. The active state of the pin is then logical “1”.

Critical event only

2 – 0 = Event output on alarm or critical temperature event (this is the default).

– 1 = Event only if the temperature is above the value in the critical temperature register (TA > TCRIT); when

the alarm window lock bit (bit6) is set, this bit cannot be altered until it is unlocked.

Event output control

3 – 0 = Event output disabled (this is the default).

– 1 = Event output enabled; when either of the lock bits (bit6 or bit7) is set, this bit cannot be altered until it

is unlocked.

Event status (read-only)(2)

4 – 0 = Event output condition is not being asserted by this device.

– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.

Clear event (write-only)(3)

5 – 0 = No effect.

– 1 = Clears the active event in interrupt mode. The pin is released and will not assert until a new interrupt

condition occurs.

Alarm window lock bit

– 0 = Alarm trips are not locked and can be altered (this is the default).

6 – 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a

logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with

a single WRITE, and do not require double WRITEs.

Critical trip lock bit

– 0 = Critical trip is not locked and can be altered (this is the default).

7 – 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a

logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with

a single WRITE, and do not require double WRITEs.

Shutdown mode

– 0 = TS is enabled, continuous conversion (this is the default).

8 – 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No

event conditions will be asserted; when either of the lock bits (bit6 or bit7) is set, then this bit cannot be

altered until it is unlocked. It can be cleared at any time.

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Doc ID 15389 Rev 5

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