ST7FMC2N6B6(2004) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

WINDOW WATCHDOG (Cont’d)

The application program must write in the

WDGCR register at regular intervals during normal

operation to prevent an MCU reset. This operation

must occur only when the counter value is lower

than the window register value. The value to be

stored in the WDGCR register must be between

FFh and C0h (see Figure 33):

– Enabling the watchdog:

When Software Watchdog is selected (by option

byte), the watchdog is disabled after a reset. It is

enabled by setting the WDGA bit in the WDGCR

register, then it cannot be disabled again except

by a reset.

When Hardware Watchdog is selected (by option

byte), the watchdog is always active and the

WDGA bit is not used.

– Controlling the downcounter :

This downcounter is free-running: it counts down

even if the watchdog is disabled. When the

watchdog is enabled, the T6 bit must be set to

prevent generating an immediate reset.

The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset (see Figure 33. Ap-

proximate Timeout Duration). The timing varies

between a minimum and a maximum value due

to the unknown status of the prescaler when writ-

ing to the WDGCR register (see Figure 34).

The window register (WDGWR) contains the

high limit of the window: to prevent a reset, the

downcounter must be reloaded when its value is

lower than the window register value and greater

than 3Fh. Figure 35 describes the window watch-

dog process.

Note: The T6 bit can be used to generate a soft-

ware reset (the WDGA bit is set and the T6 bit is

cleared).

– Watchdog Reset on Halt option

If the watchdog is activated and the watchdog re-

set on halt option is selected, then the HALT in-

struction will generate a Reset.

9.1.4 Using Halt Mode with the WDG

If Halt mode with Watchdog is enabled by option

byte (No watchdog reset on HALT instruction), it is

recommended before executing the HALT instruc-

tion to refresh the WDG counter, to avoid an unex-

pected WDG reset immediately after waking up

the microcontroller.

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