ST72324J2B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72324J2B5

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST72324

12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA.

12.5.1 General Timings

Symbol

Parameter

Conditions

tc(INST)

tv(IT)

Instruction cycle time

Interrupt reaction time 2)

tv(IT) = ∆tc(INST) + 10

fCPU=8MHz

fCPU=8MHz

12.5.2 External Clock Source

Symbol

VOSC1H

VOSC1L

tw(OSC1H)

tw(OSC1L)

tr(OSC1)

tf(OSC1)

IL

Parameter

OSC1 input pin high level voltage

OSC1 input pin low level voltage

OSC1 high or low time 3)

OSC1 rise or fall time 3)

OSCx Input leakage current

Conditions

see Figure 66

VSS≤VIN≤VDD

Figure 66. Typical Application with an External Clock Source

Min

2

250

10

1.25

Typ 1)

3

375

Max

12

1500

22

2.75

Unit

tCPU

ns

tCPU

µs

Min

Typ

VDD-1

VSS

5

Max

VDD

VSS+1

Unit

V

ns

15

±1

µA

VOSC1H

VOSC1L

90%

10%

tr(OSC1)

tf(OSC1)

tw(OSC1H)

tw(OSC1L)

EXTERNAL

CLOCK SOURCE

OSC2

OSC1

Not connected internally

fOSC

IL

ST72XXX

Notes:

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish

the current instruction execution.

3. Data based on design simulation and/or technology characteristics, not tested in production.

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