4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
Advance Information
TABLE 26: RESET TIMING PARAMETERS, VDD=3.0-3.6V (LPC MODE)
Symbol Parameter
Min
TPRST
TRSTP
TRSTF
TRST1
TRSTE
VDD stable to Reset High
100
RST# Pulse Width
100
RST# Low to Output Float
RST# High to LFRAME# Low
5
RST# Low to reset during Sector-/Block-Erase or Program
Max
48
10
1. There will be a latency due to TRSTE if a reset procedure is performed during a Program or Erase operation,
Units
µs
ns
ns
LCLK cycles
µs
T26.0 1292
VDD
RST#/INIT#
LAD[3:0]
LFRAME#
TPRST
TRSTP
TRSTF
TRSTE
TRST
Sector-/Block-Erase
or Program operation
aborted
1292 F10.0
FIGURE 10: RESET TIMING DIAGRAM (LPC MODE)
©200 Silicon Storage Technology, Inc.
30
S71292-00-000
1/06