SST49LF008C-33-4C-NH View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
SST49LF008C-33-4C-NH Datasheet PDF : 36 Pages
| |||
Advance Information
AAI Data Load Protocol
4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
TABLE 20: AAI PROGRAMMING CYCLE (INITIATED WITH WP#/AAI AT VH ONLY)
Clock Cycle Field Name Field Contents
LAD[3:0]
Comments
1
START
1110
IN
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized. The START field contents
indicate a Firmware Memory Write cycle. (1110b)
2
IDSEL
0000b to 1111b
IN
ID works identically to Firmware Memory cycle.
This field indicates which SST49LF00xC device should
respond. If the IDSEL (ID select) field matches the
value of ID[3:0], then that particular device will
respond to the whole bus cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
Only bits [19:7] for 8M, [18.7] for 4M of the total
address [27:0] are used for AAI mode. The rest are
“don’t care”.
10
MSIZE
KKKK
IN
MSIZE field is don’t care when in AAI mode
11-266
DATA
ZZZZ
IN
Data is transmitted to the device least significant nib-
ble first, from byte 0 to byte 127 as long as the RY/BY#
is high and LD# low. The host will pause the clock and
data stream when RY/BY# goes low until it returns
high, signifying that the chip is ready for more data
T20.0 1292
VH
WP#/AAI
LCLK
(Data Strobe Input)
LFRAME#
LAD[3:0]
LD#
1 2 3 4 5 6 7 8 9 10 11 12
264 266
Start
IDSEL
MADDR
Address
DATA
MSIZE
Byte 0
DATA
Byte N
DATA
Byte
N+1
DATA
Byte
2N
DATA DATA
Byte Byte
126 127
RY/BY#
FIGURE 8: AAI Load Protocol Waveform
1292 F08.0
©200 Silicon Storage Technology, Inc.
26
S71292-00-000
1/06
Share Link: 