SST34HF1622C-70-4C-L1SE View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

MFG CO.

SST34HF1622C-70-4C-L1SE

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

Silicon Storage Technology 

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

ADDRESSES AMSS-0

BES1#

TRCS

TAAS

TBES

TOHS

BES2

TBES

OE#

TBLZS

TOES

TOLZS

TBHZS

TOHZS

UBS#, LBS#

TBYLZS

TBYES

TBYHZS

DQ15-0

DATA VALID

1256 F04.0

Note: AMSS = Most Significant Address

AMSS = A16 for SST34HF1622C/S, A17 for SST34HF1622C/D/S, and A18 for SST34HF1682D

For SST34HF16x2S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA.

FIGURE 5: (P)SRAM READ CYCLE TIMING DIAGRAM

ADDRESSES AMSS3-0

WE#

BES1#

TASTS

TAWS

TWCS

TWPS

TBWS

TWRS

BES2

TBWS

UBS#, LBS#

DQ15-8, DQ7-0

TODWS

NOTE 2

TBYWS

TDSS

TOEWS

TDHS

VALID DATA IN

NOTE 2

1256 F05.0

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. AMSS = Most Significant SRAM Address

AMSS = A16 for SST34HF1622C/S, A17 for SST34HF1622C/D/S, and A18 for SST34HF1682D

For SST34HF16x2S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA.

FIGURE 6: (P)SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1

©2004 Silicon Storage Technology, Inc.

20

S71256-00-000

3/04

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