SST32HF1641C-70-4C-LS View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

MFG CO.

SST32HF1641C-70-4C-LS

Multi-Purpose Flash Plus + SRAM ComboMemory

Silicon Storage Technology 

Preliminary Specifications

Multi-Purpose Flash Plus + SRAM ComboMemory

SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281

SST32HF1621C / SST32HF1641C / SST32HF3241C

ADDRESSES AMSF-0

BEF#

OE#

WE#

DQ6 and DQ2

TOEH

TCE

TOE

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF16x1x and A20 for SST32HF32x1x

FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

1236 F10.1

ADDRESS AMS-0

SIX-BYTE CODE FOR CHIP-ERASE

5555

2AAA

5555

5555

2AAA

5555

TSCE

BEF#

OE#

WE#

TWP

DQ15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX10

SW5

Note: AMSF = Most Significant Flash Address

AMSF = A19 for SST32HF16x1x and A20 for SST32HF32x1x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 13)

X can be VIL or VIH, but no other value.

FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM

1236 F11.2

©2005 Silicon Storage Technology, Inc.

20

S71236-04-000

5/05

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