SST32HF802-70-4C-LBK View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

MFG CO.

SST32HF802-70-4C-LBK

Multi-Purpose Flash (MPF) + SRAM ComboMemory

Silicon Storage Technology 

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

ADDRESSES AMSS-0

BES#

OE#

UBS#, LBS#

DQ15-0

TRCS

TAAS

TBES

TBLZS

TOES

TOLZS

TBYES

TBYLZS

TOHS

TBHZS

TOHZS

TBYHZS

DATA VALID

Note: WE# remains High (VIH) for the Read cycle

AMSS = Most Significant SRAM Address

Data Sheet

1209 F02.0

FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM

ADDRESSES AMSS-0

WE#

BES#

TWCS

TASTS

TWPS

TBWS

TAWS

TWRS

UBS#, LBS#

DQ15-8, DQ7-0

TBYWS

TODWS

NOTE 2

TDSS

TOEWS

TDHS

VALID DATA IN

NOTE 2

1209 F03.1

Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.

If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.

Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.

FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1

©2005 Silicon Storage Technology, Inc.

13

S71209-06-000

5/05

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