SI5326C-C-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

SI5326C-C-GM

ANY FREQUENCY PRECISION CLOCK MULTIPLIER / JITTER ATTENUATOR

Silicon Laboratories 

Table 4. AC Specifications (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

PLL Performance

(fin=fout = 622.08 MHz; BW=120 Hz; LVPECL)

Lock Time

tLOCKMP Start of ICAL to of LOL

Output Clock Phase

Change

Closed Loop Jitter

Peaking

Jitter Tolerance

Phase Noise

fout = 622.08 MHz

tP_STEP

JPK

JTOL

CKOPN

After clock switch

f3  128 kHz

Jitter Frequency Loop

Bandwidth

1 kHz Offset

10 kHz Offset

100 kHz Offset

Min

—

—

—

5000/BW

—

—

—

1 MHz Offset

—

Subharmonic Noise

SPSUBH Phase Noise @ 100 kHz

—

Offset

Spurious Noise

SPSPUR

Max spur @ n x F3

—

(n  1, n x F3 < 100 MHz)

Typ

35

200

0.05

—

–106

–121

–132

–132

–88

–93

Si5326

Max

Unit

1200

ms

—

ps

0.1

dB

—

ns pk-pk

–87

–100

–104

–119

–76

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc

–70

dBc

Rev. 1.0

13

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