SI5326C-C-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

SI5326C-C-GM

ANY FREQUENCY PRECISION CLOCK MULTIPLIER / JITTER ATTENUATOR

Silicon Laboratories 

Si5326

Table 4. AC Specifications (Continued)

(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Output Rise/Fall

(20–80%) @

212.5 MHz output

Output Duty Cycle

Uncertainty @

622.08 MHz

Symbol

Test Condition

Min

CKOTRF

CMOS Output

—

VDD = 2.97

CLOAD = 5 pF

CKODC

100  Load

—

Line-to-Line

Measured at 50% Point

(Not for CMOS)

LVCMOS Input Pins

Minimum Reset Pulse tRSTMN

1

Width

Reset to Microproces-

sor Access Ready

tREADY

Input Capacitance

Cin

—

LVCMOS Output Pins

Rise/Fall Times

tRF

CLOAD = 20pf

—

See Figure 2

LOSn Trigger Window LOSTRIG From last CKINn to 

—

Internal detection of LOSn

N3 ≠ 1

Time to Clear LOL

after LOS Cleared

tCLRLOL

LOS to LOL

—

Fold = Fnew

Stable Xa/XB reference

Device Skew

Output Clock Skew

tSKEW

 of CKOUTn to  of

—

CKOUT_m, CKOUTn

and CKOUT_m at same

frequency and signal

format

PHASEOFFSET = 0

CKOUT_ALWAYS_ON = 1

SQ_ICAL = 1

Phase Change due to

tTEMP

Max phase changes from

—

Temperature Variation

–40 to +85 °C

Typ

Max

Unit

—

2

ns

—

+/-40

ps

µs

10

ms

—

3

pF

25

—

ns

—

4.5 x N3

TCKIN

10

—

ms

—

100

ps

300

500

ps

12

Rev. 1.0

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