CS8427-IS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8427-IS Datasheet PDF : 59 Pages
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CS8427
11.19 OMCK/RMCK Ratio (1Eh) (Read Only)
7
ORR7
6
ORR6
5
ORR5
4
ORR4
3
ORR3
2
ORR2
1
ORR1
0
ORR0
This register allows the calculation of the incoming sample rate by the host microcontroller from the
equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256
Fso. ORR is represented as an unsigned 2-bit integer and a 6-bit fractional part. The value is mean-
ingful only after the PLL has reached lock. For example, if the OMCK is 12.288 MHz, Fso would be
48 kHz (48 kHz = 12.288 MHz/256). Then if the input sample rate is also 48 KHz, you would get 1.0
from the ORR register.(The value from the ORR register is hexadecimal, so the actual value you will
get is 40h). If FSO/FSI > 3 63/64, ORR will saturate at the value FFh. Also, there is no hysteresis on
ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate.
ORR7:6 - Integer part of the ratio (Integer value=Integer(SRR[7:6]))
ORR5:0 - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)
11.20 C-bit or U-bit Data Buffer (20h - 37h)
Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is accessible
using these register addresses.
11.21 CS8427 I.D. and Version Register (7Fh) (Read Only)
7
6
5
4
3
2
1
0
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0
ID3:0 - ID code for the CS8427. Permanently set to 0111
VER3:0 - CS8427 revision level. Revision A is coded as 0001
38
DS477F1
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