SC4524D
switching time of the NPN transistor (see Table 4).
Table 4. Typical switching time
Input Voltage
12V
Load Current
1A
2A
12.5ns 15.3ns
W + PBST +InPaQddition, the quiescent current loss is
O
PQ = VIN ⋅ 2mA
(11)
N
⋅
IO
⋅
The
FSW
total
power
loss
of
the
SC4524D
is
therefore
P TOTAL = PC + P SW + PB ST + PQ
(12)
IO
40
Fig.9 The temPCp=erDat⋅uVrCeErSiAsTe⋅oIOf
total power dissipation
the SC4524DPisQth=eVpINro⋅ 2dmucAt of the
(Equation
(12))
and
q
JA
(36oC/W),
⋅ IO
wfohr itchhePisSSOtWhICe=-t812heE⋅rDtmSPa⋅plVaiImNck⋅pIaeOgd⋅eaF.nSWce from junction to ambient
) ⋅ I2O ⋅ R DI1Ct2i5soCnojPutBnSrTcetc=iooDnm⋅tmVeBmeSnTpd⋅ee4rIadO0tutore.oIpnetrhaeteaptphelicSaCti4o5n2s4wDithabhoigvhe
input voltage and high output current, the switching
frequePnDcy=m(1a−y Dn)e⋅eVdDt⋅oIObe reduced to meet the thermal
requirement.
PIND = (1.1 ~ 1.3) ⋅ I2O ⋅ R DC
PCB Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation, the size of the loop formed by these components
should be minimized. Since the power switch is already
integrated within the SC4524D, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
V IN
VOU T
ZL
Figure 9. Heavy lines indicate the critical pulse
current loop. The stray inductance of this
loop should be minimized.
Vin
Cu
15