PSD934F210MIT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD934F210MIT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Figure 6. Priority Level of Memory and I/O

Components

Highest Priority

Lowest Priority

Level 1

SRAM, I /O, or

Peripheral I /O

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

AI02867D

Figure 6 shows the priority levels for all memory

components. Any component on a higher level can

overlap and has priority over any component on a

lower level. Components on the same level must

not overlap. Level one has the highest priority and

level 3 has the lowest.

Memory Select Configuration for MCUs with

Separate Program and Data Spaces. The 8031

and compatible family of MCUs, which includes

the 80C51, 80C151, 80C251, and 80C51XA, have

separate address spaces for Program memory

(selected using Program Select Enable (PSEN,

CNTL2)) and Data memory (selected using Read

Strobe (RD, CNTL1)). Any of the memories within

the PSD can reside in either space or both spaces.

This is controlled through manipulation of the VM

register that resides in the CSIOP space.

The VM register is set using PSDsoft Express to

have an initial value. It can subsequently be

changed by the MCU so that memory mapping

can be changed on-the-fly.

For example, you may wish to have SRAM and pri-

mary Flash memory in the Data space at Boot-up,

and secondary Flash memory in the Program

space at Boot-up, and later swap the primary and

secondary Flash memories. This is easily done

with the VM register by using PSDsoft Express

Configuration to configure it for Boot-up and hav-

ing the MCU change it when desired.

Table 11 describes the VM Register.

Table 11. VM Register

Bit 7

PIO_EN

Bit 6

Bit 5

Bit 4

Primary

FL_Data

0 = disable

PIO mode

not used

not used

0 = RD

can’t

access

Flash

memory

1= enable

PIO mode

not used

not used

1 = RD

access

Flash

memory

Bit 3

Secondary

EE_Data

Bit 2

Primary

FL_Code

Bit 1

Secondary

EE_Code

Bit 0

SRAM_Code

0 = RD can’t

access Secondary

Flash memory

0 = PSEN

can’t

access

Flash

memory

0 = PSEN can’t

access Secondary

Flash memory

0 = PSEN

can’t

access

SRAM

1 = RD access

Secondary Flash

memory

1 = PSEN

access

Flash

memory

1 = PSEN access

Secondary Flash

memory

1 = PSEN

access

SRAM

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