PCA9541BS/03 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCA9541BS/03

2-to-1 I2C-bus master selector with interrupt logic and reset

NXP Semiconductors. 

NXP Semiconductors

PCA9541

2-to-1 I2C-bus master selector with interrupt logic and reset

Table 14. Register 2 - Interrupt Status (ISTAT) register bit description …continued

Legend: * default value

Bit Symbol

Access Value[1] Description

2

BUSOK[4]

R only 0*

no interrupt generated by bus sensor function

1

interrupt generated by bus sensor function (masked when bus

recovery/initialization requested) - Bus was not idle when the switch occurred

1

BUSINIT[4]

R only 0*

no interrupt generated by the bus recovery/initialization function

1

interrupt generated by the bus recovery/initialization function;

recovery/initialization done

0

INTIN[2]

R only 0*

no interrupt on interrupt input (INT_IN)[5]

1

interrupt on interrupt input (INT_IN)[5]

[1] Default values are the same for PCA9541/01 and PCA9541/03.

[2] Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:

INT_IN lines goes HIGH for INTIN bit

TESTON bit is cleared for MYTEST bit

NTESTON bit is cleared for NMYTEST bit

[3] Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master.

[4] BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register get cleared after a read of the same register is done. Precisely, the

register gets cleared on the second clock pulse during the read operation.

[5] If the interrupt condition remains on INT_IN after the read sequence, another interrupt will be generated (if the interrupt has not been

masked).

8.5 Power-on reset

When power is applied to VDD, an internal power-on reset holds the PCA9541 in a reset

condition until VDD has reached VPOR. At this point, the reset condition is released and the

internal registers are initialized to their default states, with:

• PCA9541/01: default Channel 0 (no STOP detect)

After power-up and/or insertion of the device in the main I2C-bus, the upstream

Channel 0 and the downstream slave channel are connected together.

• PCA9541/03: default ‘no channel’ (no STOP detect)

After power-up and/or insertion of the device in the main I2C-bus, no channel will be

connected to the downstream channel. The device is ready to receive a START

condition and its address by a master.

If either register writes to its Control Register, then the connection between the

upstream and the downstream channels is determined by the values on the Control

Registers.

Thereafter, VDD must be lowered below 0.2 V to reset the device.

PCA9541_7

Product data sheet

Rev. 07 — 2 July 2009

© NXP B.V. 2009. All rights reserved.

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