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PCA8538UG(2014) View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
MFG CO.
PCA8538UG
(Rev.:2014)
NXP
NXP Semiconductors. 
PCA8538UG Datasheet PDF : 107 Pages
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NXP Semiconductors
PCA8538
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14.3 SPI-bus timing characteristics
Table 55. SPI-bus timing characteristics
VDD1, VDD2, VDD3 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 12.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and
VIH with an input voltage swing of VSS1 to VDD1.
Symbol Parameter
Conditions
Min
Max
Unit
Pin SCL
fclk(SCL)
tSCL
tclk(H)
tclk(L)
tr
tf
Pin CE
SCL clock frequency
SCL time
clock HIGH time
clock LOW time
rise time
fall time
for SCL signal
for SCL signal
-
3.0
MHz
333
-
ns
100
-
ns
150
-
ns
-
100
ns
-
100
ns
tsu(CE_N) CE_N set-up time
th(CE_N)
CE_N hold time
trec(CE_N) CE_N recovery time
Pin SDI/SDAIN
30
-
ns
30
-
ns
30
-
ns
tsu
set-up time
set-up time for SDI data
30
-
ns
th
hold time
hold time for SDI data
30
-
ns
Pin SDO
td(R)SDO
tdis(SDO)
tt(SDI-SDO)
SDO read delay time
SDO disable time
transition time from SDI to
SDO
CL = 100 pF
to avoid bus conflict
-
[1] -
0
150
ns
50
ns
-
ns
[1] No load value; bus will be held up by bus capacitance; use RC time constant with application values.
PCA8538
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
80 of 107

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