PCA8538UG(2014) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCA8538UG
(Rev.:2014)

Automotive 102 x 9 Chip-On-Glass LCD segment driver

NXP Semiconductors. 

NXP Semiconductors

PCA8538

Automotive 102 x 9 Chip-On-Glass LCD segment driver

8.6.3 Internal clock

In applications where the internal clock is used, the input pin OSC must be connected to

VSS1. It is possible to make the clock frequency available on pin CLK by setting bit COE

logic 1 (see Table 10 on page 11). If pin CLK is not used, it should be left open. At

power-on the signal at pin CLK is disabled and pin CLK is in 3-state.

8.6.4 Command: Frame-frequency

With this command the clock and frame frequency can be programmed when using the

internal clock.

Table 23. Frame-frequency - frame frequency select command bit description

Bit

Symbol

Value

Description

-

R/W

0

fixed value

-

RS[1:0]

00

fixed value

7 to 5 -

111

fixed value

4 to 0 FF[4:0]

see Table 24 clock and frame frequency (Hz)

The duty ratio of the clock output may change when choosing different values for the

frame frequency (see Table 24).

The LCD frame frequency is derived from the clock frequency by a fixed division (see

Equation 1).

ffr

=

-f--c--l--k-

144

(1)

The Frame-frequency command allows configuring the frame frequency in the range of

45 Hz to 300 Hz with steps of

• 5 Hz from 45 Hz to 100 Hz

• 10 Hz from 100 Hz to 300 Hz

The default frame frequency of 80 Hz is factory calibrated with a tolerance of 3 Hz at

25 C.

Table 24. Clock and frame frequency values

Duty cycle definition: % HIGH-level time : % LOW-level time.

FF[4:0] Frame frequency (Hz) Clock frequency (Hz)

00000 45

6472

00001 50

7200

00010 55

7945

00011 60

8662

00100 65

9366

00101 70

10105

00110 75

10766

00111[1] 80

11520

01000 85

12255

01001 90

12944

01010 95

13714

Typical duty cycle (%)[1]

29 : 71

20 : 80

12 : 88

4 : 96

48 : 52

44 : 56

41 : 59

36 : 64

32 : 68

29 : 71

24 : 76

PCA8538

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 26 September 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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