MT90823
Data Sheet
AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2)
Characteristics
Sym. Min. Typ. Max. Units Test Conditions
1 AS pulse width
tASW
20
2 Address setup from AS falling
tADS
3
3 Address hold from AS falling
tADH
3
4 Data setup from DTA Low on Read
tDDR
5
5 CS hold after DS falling
tCSH
0
6 CS setup from DS rising
tCSS
0
7 Data hold after write
tDHW
5
8 Data setup from DS -Write (fast write) tDWS
20
9 Valid Data Delay on write (slow write) tSWD
10 R/W setup from DS rising
tRWS
60
11 R/W hold after DS falling
tRWH
5
12 Data hold after read
tDHR
10
ns
ns
ns
ns CL=150pF
ns
ns
ns
ns
122
ns
ns
ns
20
ns CL=150pF, RL=1K,
Note 1
13 DS delay after AS falling
tDSH
10
14 Acknowledgment Delay:
tAKD
Reading/Writing Registers
Reading/Writing Memory @ 2Mb/s
@ 4Mb/s
@ 8Mb/s
15 Acknowledgment Hold Time
tAKH
ns
43/43
760/750
400/390
220/210
22
ns CL=150pF
ns CL=150pF
ns CL=150pF
ns CL=150pF
ns CL=150pF, RL=1K,
Note 1
Note 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Zarlink Semiconductor Inc.