MT90823
Data Sheet
AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1)
Characteristics
Sym. Min. Typ. Max. Units Test Conditions
1 ALE pulse width
tALW
20
2 Address setup from ALE falling
tADS
3
3 Address hold from ALE falling
tADH
3
4 RD active after ALE falling
tALRD
3
5 Data setup from DTA Low on Read
tDDR
5
6 CS hold after RD/WR
tCSRW
5
7 RD pulse width (fast read)
tRW
45
8 CS setup from RD
tCSR
0
9 Data hold after RD
tDHR
10
ns
ns
ns
ns
ns CL=150pF
ns
ns
ns
20
ns CL=150pF, RL=1K,
Note 1.
10 WR pulse width (fast write)
tWW
45
11 WR delay after ALE falling
tALWR
3
12 CS setup from WR
tCSW
0
13 Data setup from WR (fast write)
tDSW
20
14 Valid Data Delay on write (slow write) tSWD
15 Data hold after WR inactive
tDHW
5
16 Acknowledgment Delay:
tAKD
Reading/Writing Registers
Reading/Writing Memory @ 2Mb/s
@ 4Mb/s
@ 8Mb/s
17 Acknowledgment Hold Time
tAKH
122
43/43
760/750
400/390
220/210
22
ns
ns
ns
ns
ns
ns
ns CL=150pF
ns CL=150pF
ns CL=150pF
ns CL=150pF
ns CL=150pF, RL=1K,
Note 1.
Note:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Zarlink Semiconductor Inc.