M25PE80-VMN6TP View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

MFG CO.

M25PE80-VMN6TP

8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout

Numonyx -> Micron 

Instructions

6

Instructions

M25PE80

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most

significant bit first, on serial data input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 6.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),

Read Identification (RDID), Read Status Register (RDSR), or Read Lock Register (RDLR)

instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip

Select (S) can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a Page Write (PW), Page Program (PP), Write to Lock Register (WRLR),

Page Erase (PE), SubSector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write

Enable (WREN), Write Disable (WRDI), Write Status Register (WRSR), Deep Power-down

(DP) or Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven

High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.

That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select

(S) being driven Low is an exact multiple of eight.

All attempts to access the memory array during a write cycle, program cycle or erase cycle

are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected.

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