LTC6912C-1 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC6912C-1 Datasheet PDF : 24 Pages
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LTC6912
APPLICATIO S I FOR ATIO
configuration. It is recommended the serial interface sig-
nals should remain idle in between data transfers in order
to minimize digital noise coupling into the analog path.
Power On Reset
On the initial application of power, the power on reset
state of both amplifiers is low power software shutdown
(state = 8) (see Tables 1 and 2). In this state, both analog
amplifiers are disabled and have their inputs and outputs
opened. This will facilitate the application of using the
device as a 2:1 analog MUX, in that the amplifier’s outputs
may be wired-OR together and the LTC6912 can alter-
nately select between A and B channels. Care must be
taken if the outputs are wired-OR’d to ensure the software
shutdown state (state = 8) is always programmed in one
of the two channels.
Timing Constraints
Settling time in the CMOS gain-control logic is typically
several nanoseconds and is faster than the analog signal
path. When the amplifier gain changes, the limiting timing
is analog. As with any programmable-gain amplifier, each
gain change causes an output transient as the amplifier’s
output moves, with finite speed, toward a differently
scaled version of the input signal. The LTC6912-X analog
path settles with a characteristic time constant or time
scale, τ, that is roughly the standard value for a first order
band limited response:
τ = 0.35/f–3dB
See the –3dB BW vs Gain Setting graph in the Typical
Performance Characteristics section.
SINGLE-POINT
SYSTEM GND
CS/LD
µP DATA
CLK
1
16
2 LTC6912-X 15 0.1µF
3
14 V–
4
5 SHDN
6 CS/LD
7 DIN
8
13 0.1µF
12 V+
11
10
DGND
DOUT 9
ANALOG GROUND PLANE
1
16
2 LTC6912-X 15 0.1µF
3
14 V–
4
5 SHDN
6 CS/LD
7 DIN
8
13 0.1µF
12 V+
11
10
DGND
DOUT 9
DIGITAL GROUND PLANE
CLK
DIN
CS/LD
D15
D11 D10 D9 D8 D7
D3 D2 D1 D0
6912 F06
Figure 6. Two LTC6912s (Four PGAs) in Daisy Chain Configuration
6912fa
20
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