LTC3403EDD View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3403EDD Datasheet PDF : 16 Pages
| |||
APPLICATIO S I FOR ATIO
Reductions in power dissipation occur at higher supply
voltages, where the junction temperature is lower due to
reduced switch resistance (RDS(ON)). Further reductions
may be achieved using an external bypass FET (Figure 5),
which operates in parallel with the network described
above.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (ILOAD • ESR), where ESR is the effective series
resistance of COUT. ILOAD also begins to charge or dis-
charge COUT, which generates a feedback error signal. The
regulator loop then acts to return VOUT to its steady state
value. During this recovery time VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. For a detailed explanation of switching control loop
theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • CLOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
LTC3403
LTC3403
VIN
VIN
SW
GDR
VOUT
M1
VOUT
LTC3403 F05
Figure 5. Driving an External Bypass FET
VIN
CIN
1
GDR
2
VIN
3 GND
4
SW
8
VOUT
7
REF
6
MODE
5
RUN
LTC3403
VOUT
COUT
RREF
DAC
CREF
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 6.Layout Diagram
LTC3403 F06
3403f
13
Share Link: 