LTC3403EDD View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3403EDD Datasheet PDF : 16 Pages
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LTC3403
APPLICATIO S I FOR ATIO
1. The VIN quiescent current consists of two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from VIN to ground. The resulting dQ/dt is typically larger
than the DC bias current. In continuous mode, IGATECHG =
f(QT + QB), where QT and QB are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VIN, thus, their
effects will be more pronounced at higher supply voltages.
(The gate charge of the bypass FET is, of course, negligible
because it is infrequently cycled.)
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In con-
tinuous mode, the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Charateristics
curves. Hence, to obtain I2R losses, simply add RSW to RL
and multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3403 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3403 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To prevent the LTC3403 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC3403 in dropout at an
input voltage of 2.7V, a load current of 600mA (0.9V ≤ VREF
< 1.2V) and an ambient temperature of 70°C. With VREF <
1.2V, the entire 600mA flows through the main P-channel
FET. From the typical performance graph of switch resis-
tance, the RDS(ON) of the P-channel switch at 70°C is
approximately 0.52Ω. Therefore, power dissipated by the
part is:
PD = (ILOAD2) • RDS(ON) = 187.2mW
For the 8L DFN package, the θJA is 43°C/W. Thus, the
junction temperature of the regulator is:
TJ = 70°C + (0.1872)(43) = 78°C
which is below the maximum junction temperature of
125°C.
Modifying this example, suppose that VREF is raised to
1.2V or higher. This turns on the bypass P-channel FET as
well as the main P-channel FET. Assume that the inductor’s
DC resistance is 0.1Ω, the RDS(ON) of the main P-channel
switch is 0.52Ω, and the RDS(ON) of the bypass P-channel
switch is 0.21Ω. The current through the P-channel switch
and the inductor will be 152mA, causing power dissipation
of (0.152A)2 • 0.62Ω = 14.3mW. The bypass FET will
dissipate (0.448A)2 • 0.21Ω = 42.5mW. Thus, TJ = 70°C +
(0.0143 + 0.0425)(43) = 72.4°C.
3403f
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