LTC2202(RevB) View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC2202 Datasheet PDF : 32 Pages
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LTC2203/LTC2202
APPLICATIO S I FOR ATIO
PGA Pin
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.5VP-P; PGA =
1 selects an input range of 1.667VP-P. The 2.5V input range
has the best SNR; however, the distortion will be higher for
input frequencies above 100MHz. For applications with high
input frequencies, the low input range will have improved
distortion; however, the SNR will be 2.4dB worse. See the
Typical Performance Characteristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with a
low-jitter squaring circuit before the CLK pin (Figure 8).
SINUSOIDAL
CLOCK
INPUT
4.7μF
CLEAN 3.3V
SUPPLY
FERRITE
BEAD
0.1μF
0.1μF 1k
CLK
LTC2203/02
56Ω 1k NC7SVU04
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Figure 8. Sinusoidal Single-Ended CLK Drive
The noise performance of the LTC2203/2202 can depend
on the clock signal quality as much as on the analog
input. Any noise present on the clock signal will result in
additional aperture jitter that will be RMS summed with
the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. It is also helpful to drive the CLK pin with a
low-jitter high frequency source which has been divided
down to the appropriate sample rate. If the ADC is clocked
with a sinusoidal signal, filter the CLK signal to reduce
wideband noise and distortion products generated by
the source.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2203 is 25Msps.
The maximum conversion rate for the LTC2202 is 10Msps.
For the ADC to operate properly the CLK signal should have
a 50% (±5%) duty cycle. Each half cycle must have at least
18.9ns for the LTC2203 internal circuitry to have enough
settling time for proper operation. For the LTC2202, each
half cycle must be at least 40ns.
An on-chip clock duty cycle stabilizer may be activated if
the input clock does not have a 50% duty cycle. This circuit
uses the falling edge of CLK pin to sample the analog input.
The rising edge of CLK is ignored and an internal rising
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2203/LTC2202 sample rate is
determined by droop of the sample and hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operating
frequency for the LTC2203/LTC2202 is 1Msps.
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