CS8422 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8422

24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver

Cirrus Logic 

CS8422

DETC - D to E C-buffer transfer interrupt.

Indicates the completion of a D to E C-buffer transfer. See “Channel Status Buffer Management” on page

53.

CCH - C-Data change.

Indicates that the current 10 bytes of channel status is different from the previous 10 bytes. (5 bytes per

channel)

RERR - A receiver error has occurred.

The Receiver Error register may be read to determine the nature of the error which caused the interrupt.

QCH – A new block of Q-subcode is available for reading.

The data must be read within 588 AES3 frames after the interrupt occurs to avoid corruption of the data

by the next block.

FCH – Format Change

Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL bits in the Format Detect Status

register transition from 0 to 1. When these bits in the Format Detect Status register transition from 1 to 0,

an interrupt will not be generated.

SRC_UNLOCK - SRC Unlock condition.

Indicates that the SRC has lost the ability to output valid data

11.21 PLL Status (15h)

7

6

5

RX_ACTIVE

ISCLK

ACTIVE

PLL_LOCK

4

96KHZ

3

192KHZ

2

Reserved

1

Reserved

0

Reserved

RX_ACTIVE - Receiver Active

This bit is a level-signal version of the ACTIVE bit in register 13h.

ISCLK_ACTIVE- ISCLK Active

0 - There is no toggling on the ISCLK pin, or the frequency of toggling is less than 36 kHz on the ISCLK

pin.

1 - There is toggling at a frequency of at least 1.536 MHz on the ISCLK pin.

PLL_LOCK -

0 - The PLL has not achieved lock.

1 - The PLL, driven by either an AES3 or ISCLK input, has achieved lock.

96KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi  49 kHz or

Fsi  120 kHz, this bit will output a “0”. If 60 kHz Fsi 98 kHz, this bit will output a “1”. Otherwise the output

is indeterminate.

192KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi  98 kHz,

this bit will output a “0”. If Fsi 120 kHz, this bit will output a “1”. Otherwise the output is indeterminate.

60

DS692F1

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