TCBL
Tth
VLRCK
U
U[0]
CS8406
U[2]
SDIN
Data [4]
Data [5]
Data [6]
Data [7]
Data [8]
TXP(N)
Z
Data [0]*
* Assume MMTLR = 0
Y
Data [2]*
X
Data [4]*
TXP(N)
Z
Data [1]*
Y
Data [3]*
X
Data [5]*
Note:
1.
2.
3.
* Assume MMTLR = 1
Tsetup ≥ 15% AES3 frame rate
Thold = 0
Tth > 3 OMCKS if TCBL is an input
Figure 9. AES3 Transmitter Timing for C, U, and V Pin Input Data, Mono Mode
DS580F5
15