CS7620 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS7620 Datasheet PDF : 70 Pages
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CS7620
4.51 Power_up Counter
Default = 7Dh; Read/Write (address 3Dh)
Bit Number
Bit Name
Default
7
cnt_reg7
0
6
cnt_reg6
1
5
cnt_reg5
1
4
cnt_reg4
1
3
cnt_reg3
1
2
cnt_reg2
1
1
cnt_reg1
0
0
cnt_reg0
1
Bit
Mnemonic
Function
7
cnt_reg7
Power Up Counter Register: When coming out of power down, there is a pe-
6
cnt_reg6
riod of time required for voltages and currents to settle to the proper values,
5
cnt_reg5
for the PLL to lock, and for the gain calibration to be performed. This should
all be accomplished within 500 µs. The pixel clocks required to meet this 500
4
cnt_reg4
µs time should be programmed into this register. Note that if the master clock
3
cnt_reg3
is being divided on chip, the divider’s output clock is the pixel clock.
2
cnt_reg2
1
cnt_reg1
0
cnt_reg0
4.52 Valid_data/Dout Edge/Clock_in Divider
Default = 01h; Read/Write (address 3Fh)
Bit Number
Bit Name
Default
7
Reserved
-
6
valid_data
0
5
4
3
2
1
0
dout_edge clk_divide4 clk_divide3 clk_divide2 clk_divide1 clk_divide0
0
0
0
0
0
1
Bit
Mnemonic
Function
7
-
Reserved
Valide Data Mode: This mode will redefine the CLKO pin as a data valid pin.
The data_valid signal will only toggle over active pixels and is phase-aligned
with the master clock. The user may then latch the data during this valid time
using the master clock or a clock derived from it. Note that this mode may only
be used if the master clock frequency is an integer multiple greater than 1 of
6
valid_data
the pixel rate (see Figures 14 and 15).
If this mode is not selected, the output clock is output on the CLKO pin.
0 - digital clock output on CLKO pin
1 - valid_data signal on CLKO pin
Dout Edge Selelction: If valid_data = 0, the edge of the clock that clocks out
the data is selected by this bit. The data may be output either on the rising or
the falling edge of the output clock, CLKO. HSYNC and RD_OUT are also out-
5
dout_edge
put on same edge.
Note that If valid_data = “1”, this register is invalid.
* HSYNC and RD_OUT also output on the same edge
DS301PP2
61
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