CS7620 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS7620 Datasheet PDF : 70 Pages
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CS7620
4.33 Horizontal Timing Control - H4
Default = 1Eh; Read/Write (address 2Ch)
Bit Number
Bit Name
Default
7
6
5
Reserved
h4d
h4f_reg2
-
0
0
4
h4f_reg1
1
3
h4f_reg0
1
2
h4f_reg2
1
1
h4f_reg1
1
0
h4f_reg0
0
Bit
Mnemonic
Function
7
-
Reserved
During the vertical shift time, the horizontal clocks are held in one state. This
bit controls whether H4 is held high or low during this time.
6
h4d
A “0” indicates that the signal state is low, a “1” indicates that the signal state
is high.
5
h4f_reg2
The phase of the falling edge of H4 can be programmed through this register.
4
h4f_reg1
The falling edge of H4 corresponds to the rising edge of the internally selected
clock. The phases of these clocks in shown in Figure 19, with the complement-
ed clocks being the inverse of these (i.e. the falling edge of p1 is the rising
edge of p1, etc.).
3
h4f_reg0
0 = t0
1 = t1
2 = t2
3 = t3
4 = t4
5 = t5
6 = t6
7 = t7
(See Figure 19)
2
h4f_reg2
The phase of the rising edge of H4 can be programmed through this register.
1
h4f_reg1
The rising edge of H4 corresponds to the rising edge of the internally selected
clock. The phases of these clocks in shown are Figure 19, with the comple-
mented clocks being the inverse of these.
0
h4f_reg0
0 = t0
1 = t1
2 = t2
3 = t3
4 = t4
5 = t5
6 = t6
7 = t7
(See Figure 19)
DS301PP2
51
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