CS7620-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS7620-IQ Datasheet PDF : 70 Pages
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CS7620
4.18 Timing Control - Start of Black Pixels
Default = 04h; Read/Write (address 1Ch)
Bit Number
Bit Name
Default
7
6
5
Reserved
-
-
-
4
3
2
1
0
blk_begin3 blk_begin2 blk_begin1 blk_begin0
-
0
1
0
0
Bit
Mnemonic
Function
7:4
-
Reserved
3
blk_begin3
Black Pixels: This register indicates the beginning of the black pixels within
2
blk_begin2
a horizontal line.
1
blk_begin1
Before the black pixels, there can be some extra pixels, due to latency through
the horizontal shift register inside the CCD. The default value for this register
0
blk_begin0
is 4, since IBM35CCD2PIX1 has 3 extra pixels. (See Figure 28)
4.19 Timing Control - End of Black Pixels
Default = 3Fh; Read/Write (address 1Dh)
Bit Number
Bit Name
Default
7
Reserved
-
6
blk_end6
0
5
blk_end5
1
4
blk_end4
1
3
blk_end3
1
2
blk_end2
1
1
blk_end1
1
0
blk_end0
1
Bit
Mnemonic
Function
7
-
Reserved
6
blk_end6
Black Pixels: This register indicates the end of the black pixels within the hor-
5
blk_end5
izontal line.
4
blk_end4
This register is used by the black level loop together with blk_begin, to acquire
3
blk_end3
the proper black level on a line by line basis. Since the loop has some latency,
2
blk_end2
the value stored in this register, should be 10 less than the actual last black
pixel in each line. Since in IBM35CCD2PIX1, this number is 73, the default is
1
blk_end1
set to 63. (See Figure 28)
0
blk_end0
40
DS301PP2
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