CS7620-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS7620-IQ Datasheet PDF : 70 Pages
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CS7620
4.1 Reset
Default = 00; Write (address 00h)
Bit Number
Bit Name
Default
7
6
5
4
3
2
1
0
Reserved
sft_rst
-
-
-
-
-
-
-
00
Bit
Mnemonic
Function
7:1
-
Reserved
Software Reset: When this bit is written with a ‘1’, all of the digital circuitry
0
sft_rst
and the registers will reset to their default values. It automatically clears after
4 pixel clock periods. The clocks remain running during the reset period.
4.2 Power Down Control 1
Default = 00h; Read/Write (address 01h)
Bit Number
Bit Name
Default
7
pd_vga
0
6
pd_adc
0
5
pd_ref
0
4
3
Reserved
-
-
2
pd_dac1
0
1
pd_dac2
0
0
Reserved
-
Bit
Mnemonic
Function
7
pd_vga
DRX Front End Power Down: When written with a ‘1’, the DRX front end
circuitry powers down. Used for test purposes only.
ADC Power Down: When written with a ‘1’, the Analog-to-Digital converter
6
pd_adc
circuitry powers down. Used for test purposes only.
5
pd_ref
Voltage Reference Power Down: When written with a ‘1’, the voltage refer-
ence generator powers down. Used for test purposes only.
4:3
-
Reserved
DAC #1 Power Down: When written with a ‘1’, DAC #1 powers down. Should
2
pd_dac1
be powered down when DAC#1 is not being used by the system.
1
pd_dac2
DAC #2 Power Down: When written with a ‘1’, DAC #2 powers down. Should
be powered down when DAC#2 is not being used by the system.
0
-
Reserved
28
DS301PP2
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