CS5581(2007) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5581
(Rev.:2007)

±2.5 V / 5 V, 200 kSps, 16-bit, High-throughput ∆Σ ADC

Cirrus Logic 

8/21/07

15:56

CS5581

The RDY signal falls upon completion of reset and calibration sequence. If CAL remains low when RST

transitions from low to high, no calibration will be performed. Calibrations can be initiated any time the

converter is idle by taking the CAL input high. RDY will fall at the end of the calibration cycle. The CAL pin

should be returned low when not being used.

A calibration cycle calibrates the offset and full-scale points of the converter transfer function. When the

offset portion of the calibration is performed, the AIN and ACOM pins are disconnected from the input and

shorted internally. The offset of the converter is then measured and a correction factor is stored in a reg-

ister. Then the voltage reference is internally connected to act as the input signal to the converter and a

gain calibration is performed. The gain correction results are also placed in a register. The contents of the

offset and gain registers are used to map the conversion data prior to its output from the converter.

3.2 Performing Conversions

The CS5581 converts at 200 kSps when synchronously operated (CONV = VLR) from a 16.0 MHz master

clock. Conversion is initiated by taking CONV low. A conversion lasts 80 master clock cycles, but if CONV

is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to when a

conversion actually begins. This may extend the throughput to 84 MCLKs per conversion.

When the conversion is completed, the output word is placed into the serial port and RDY goes low. To

convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a

conversion is performed in 80 MCLK cycles. Alternately RDY can be tied to CONV and a conversion will

occur every 82 MCLK cycles.

To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY

falls.

Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are

emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two

MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data

is put into the port register.

See Serial Port on page 23 for information about reading conversion data.

Conversion performance can be affected by several factors. These include the choice of clock source for

the chip, the timing of CONV, and the choice of the serial port mode.

The converter can be operated from an internal oscillator. This clock source has greater jitter than an

external crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-fre-

quency AC signals, but can become an issue for higher frequency AC signals. For maximum performance

when digitizing AC signals, a low-jitter MCLK should be used.

To maximize performance, the CONV pin should be held low in the continuous conversion state to per-

form multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls.

When performing conversions on an AC signal, CONV should be held low in the continuous conversion

state to perform multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK

falls.

If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in-

terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer-

ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a

conversion is not is progress.

14

DS796A1

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