CS5560-ISZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5560-ISZ

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

7/31/07

CS5560

VLR, VL – Logic Interface Power/Return, Pin 20, 21

VL and VLR are the supply voltages for the digital logic interface. VL and VLR can be config-

ured with a wide range of common mode voltage. The following interface pins function from the

VL/VLR supply: SMODE, CS, SCLK, SDI, SDO, RDY, SLEEP, CONV, RST, CONV, CAL,

BP/UP, and MCLK.

SDO – Serial Data Output, Pin 22

SDO is the output pin for the serial output port. Data from this pin will be output at a rate deter-

mined by SCLK and in a format determined by the BP/UP pin. Data is output MSB first and

advances to the next data bit on the rising edges of SCLK. SDO will be in a high impedance

state when CS is high.

SCLK – Serial Clock Input/Output, Pin 23

The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK

determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC

mode, the SCLK frequency will be determined by the master clock frequency of the converter

(either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency.

If SMODE = VL (SSC Mode), SCLK will be in a high-impedance state when CS is high.

RDY – Ready, Pin 24

The RDY signal rises when a calibration is initiated. When the calibration is near completion the

state of CONV is examined. If CONV is high, the RDY signal will fall upon the completion of cal-

ibration. If CONV is low the converter will immediately start a conversion and RDY will remain

high until the conversion is completed. At the end of any conversion RDY falls to indicate that a

conversion word has been placed into the serial port. RDY will return high after all data bits are

shifted out of the serial port or two master clock cycles before new data becomes available if the

CS pin is inactive (high); or two master clock cycles before new data becomes available if the

user holds CS low but has not started reading the data from the converter when in SEC mode.

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DS713A5

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