CS5560-ISZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5560-ISZ

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

7/31/07

CS5560

3.8 AIN & VREF Sampling Structures

The CS5560 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher

input impedance and therefore reduce the amount of drive current required from an external source. This

helps minimize errors.

The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is

connected to the V1+ supply the buffers will be enabled. If the BUFEN pin is connected to the V1- pin

the buffers are off. The converter will consume about 30 mW less power when the buffers are off, but the

input impedances of AIN+, AIN- and VREF+ will be significantly less than with the buffers enabled.

3.9 Converter Performance

The CS5560 achieves excellent differential nonlinearity (DNL) as shown in Figure 9. Figure 9 illustrates

the code widths on the typical scale of ±1 LSB and on a zoomed scale of ±0.2 LSB.

Figure 9. CS5560 DNL Plot

(Zoom View)

22

DS713A5

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