CS5560 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5560

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

7/31/07

CS5560

The on-chip calibration registers can be read or written via the serial port. Reading or writing into the cal-

ibration registers requires that the serial port be in the SEC mode. To write into the offset or gain register,

the appropriate 8-bit command (see Table 1 on page 16) is first shifted into the SDI pin. Rising edges of

SCLK latch the bits. To perform a write, the 8-bit command is immediately followed by the 24 bit data word

to be written. When a read command is used, the 24 bit data word from the register will be output from

the SDO pin. The data bits will be output on rising edges of SCLK. The data bits have sufficient hold time

to be latched externally by the next rising edge of SCLK.

3.2 Conversion

The CS5560 converts at 50 kSps when synchronously operated (CONV = VLR) from a 16.0 MHz master

clock. Conversion is initiated by taking CONV low. A conversion lasts 320 master clock cycles, but if

CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to

when a conversion actually begins. This may extend the throughput to 324 MCLKs

When the conversion is completed, the output word is placed into the serial port and RDY goes low. To

convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a

conversion is performed in 320 MCLK cycles. Alternately RDY can be tied to CONV and a conversion will

occur every 322 MCLK cycles.

To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY

falls.

Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are

emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two

MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data

is put into the port register.

See Serial Port on page 24 for information about reading conversion data.

Conversion performance can be affected by several factors. These include the choice of clock source for

the chip, the timing of CONV, and the choice of the serial port mode.

The converter can be operated from an internal oscillator. This clock source has greater jitter than an

external crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-fre-

quency AC signals, but can become an issue for higher frequency AC signals. For maximum performance

when digitizing AC signals, a low-jitter MCLK should be used.

To maximize performance, the CONV pin should be held low in the continuous conversion state to per-

form multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls.

If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in-

terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer-

ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a

conversion is not is progress.

3.3 Clock

The CS5560 can be operated from its internal oscillator or from an external master clock. The state of

MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and

be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK

the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held

high, the internal oscillator will be held in the stopped state. The MCLK input can be held high to delete

clock cycles to aid in operating multiple converters in different phase relationships.

DS713A5

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