CS5560 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5560

±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC

Cirrus Logic 

7/31/07

CS5560

2. OVERVIEW

The CS5560 is a 24-bit analog-to-digital converter capable of 50 kSps conversion rate. The device is ca-

pable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a

low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in

one conversion.

The converter is a serial output device. The serial port can be configured to function as either a master or

a slave.

The CS5560 provides self-calibration circuitry to achieve low offset and gain errors.

The converter can operate from an analog supply of 5V or from ±2.5V. The digital interface supports stan-

dard logic operating from 1.8, 2.5, or 3.3 V.

The CS5560 converts at 50 kSps when operating from a 16 MHz input clock.

3. THEORY OF OPERATION

The CS5560 converter provides high-performance measurement of DC or AC signals. The converter in-

cludes on-chip calibration circuitry to minimize offset and gain errors. The converter can be used to per-

form single conversions or continuous conversions upon command. Each conversion is independent of

previous conversions and can settle to full specified accuracy, even with a full-scale input voltage step.

This is due to the converter architecture which uses a combination of a high-speed delta-sigma modulator

and a low-latency filter architecture.

Once power is established to the converter, a reset must be performed. A reset initializes the internal con-

verter logic and sets the offset register to zero and the gain register to a decimal value of 1.0. If the CAL

pin is low when RST transitions from low to high, no calibration will be performed. If CAL is high when RST

goes high, the converter’s offset & gain slope will be calibrated.

If CONV is held low then the converter will convert continuously with RDY falling every 320 MCLKs. This

is equivalent to 50 kSps if MCLK = 16.0 MHz. If CONV is tied to RDY, a conversion will occur every 322

MCLKs. If CONV is operated asynchronously to MCLK, it may take up to 324 MCLKs from CONV falling

to RDY falling.

Multiple converters can operate synchronously if they are driven by the same MCLK source and CONV

to each converter falls on the same MCLK falling edge. Alternately, CONV can be held low and all devices

are reset with RST rising on the same falling edge of MCLK.

The output coding of the conversion word is a function of the BP/UP pin.

The active-low SLEEP signal causes the device to enter a low-power state. The calibration register con-

tents are preserved during sleep. When exiting sleep, the converter will take 3083 MCLK cycles before

conversions can be performed. RST should remain inactive (high) when SLEEP is asserted (low).

3.1 Reset and Calibration

After the power supplies and the voltage reference are stable, the converter must be reset. The reset func-

tion initializes the internal logic in the converter, but does not initiate calibration. After reset has been per-

formed, the converter can be used uncalibrated, or calibration can be performed. Calibration minimizes

offset and gain errors inside the converter. If the device is used without calibration, conversions will in-

clude the offset and gain errors of the uncalibrated converter, but the converter will maintain its differential

and integral linearity. Calibration of offset and gain can be performed upon command.

DS713A5

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