CS5376A
23.1.1 SPI1CTRL : 0x00, 0x01, 0x02
(MSB) 23
--
R/W
0
Figure 43. SPI 1 Control Register SPI1CTRL
22
21
20
19
18
17
--
--
--
--
--
--
R/W1
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
1
15
14
SMODF
--
R
R/W
0
0
13
12
11
10
9
--
EMOP
SWEF
--
--
R
R
R
R/W
R/W
0
0
0
0
1
7
6
5
4
3
2
1
--
--
--
--
--
--
--
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
0
16
--
R/W
1
8
E2DREQ
R/W
0
(LSB) 0
--
R/W
0
SPI 1 Address: 0x00
0x01
0x02
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:16 --
reserved
15 SMODF SPI 1 mode fault flag 7:0 --
14:13 --
reserved
12 EMOP External master to SPI 1
operation in progress
flag
11 SWEF SPI 1 write collision
error flag
10:9 --
reserved
8 E2DREQ External master to digital
filter request flag
reserved
83