CS5376A(2004) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376A Datasheet PDF : 107 Pages
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CS5376A
23.2.4 SPI2CTRL : 0x10
Figure 50. SPI 2 Control Register SPI2CTRL
(MSB) 23
WOM
R/W
0
22
SCKFS2
R/W
0
21
SCKFS1
R/W
1
20
SCKFS0
R/W
1
19
SPI2EN3
R/W
1
18
SPI2EN2
R/W
1
17
SPI2EN1
R/W
1
16
SPI2EN0
R/W
1
15
RCH1
R/W
0
14
RCH0
R/W
0
13
D2SOP
R
0
12
SCKPH
R/W
0
11
SWEF
R/W
0
10
SCKPO
R/W
0
9
8
TM
D2SREQ
R/W
R/W
0
0
7
6
5
4
3
2
1
(LSB) 0
DNUM2
DNUM1
DNUM0
CS4
CS3
CS2
CS1
CS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
0
0
0
0
DF Address: 0x10
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable
and Writable
Bits in bottom rows
are reset condition.
Bit definitions:
23 WOM Wired-or mode
15:14 RCH
1: Enabled (open drain)
[1:0]
0: Disabled (push-pull)
Read channel
11: SI4
10: SI3
01: SI2
00: SI1
7:5 DNUM Number of bytes in
[2:0]
serial transaction
22:20 SCKFS SCK2 frequency select 13 D2SOP Digital filter to SPI2 4 CS4
[2:0]
111: reserved
operation in progress
110: reserved
flag
101: 4.096 MHz
100: 2.048 MHz
011: 1.024 MHz
010: 512 kHz
001: 128 kHz
12 SCKPH SO output timing
3 CS3
1: Data becomes valid
on first SCK2 edge
2 CS2
0: Data becomes valid
000: 32 kHz
before first SCK2 edge
Chip Select 4 Enable
Chip Select 3 Enable
Chip Select 2 Enable
11 SWEF SPI2 write collision flag 1 CS1
19:16 SPI2EN SI[4:1] input enable 10 SCKPO SCK2 data polarity
0
CS0
[3:0]
1111: All enabled
1: Valid on falling edge,
0000: All disabled
transition on rising edge
0: Valid on rising edge,
transition on falling edge
Chip Select 1 Enable
Chip Select 0 Enable
9 TM
SPI2 timeout flag
1: SPI2 timed out
0: not timed out
8 D2SREQ Digital filter to SPI2
serial transaction request
1: Request operation
0: Operation complete
(cleared by hardware)
91
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