SWITCHING CHARACTERISTICS
CLK, SYNC, MCLK, MSYNC, and MDATA
SYNC
CS5378
MCLK
MSYNC
MDATA
tmsd
tmsh
tmsd
Data1
Data2
Note: SYNC input latched on MCLK rising edge. MSYNC output triggered by MCLK falling edge.
fMCLK
tmsd = TMCLK / 4
tmsh = TMCLK
2.048 MHz
tmsd = 122 ns
tmsh = 488 ns
1.024 MHz
tmsd = 244 ns
tmsh = 976 ns
Figure 7. SYNC, MCLK, MSYNC, MDATA Interface Timing
Parameter
Master Clock Frequency
Master Clock Duty Cycle
Master Clock Rise Time
Master Clock Fall Time
Master Clock Jitter
Synchronization after SYNC rising
MSYNC Setup Time to MCLK rising
MCLK rising to Valid MDATA
MSYNC falling to MCLK rising
Symbol Min
Typ
Max Unit
(Note 3) CLK
32
32.768 33
MHz
DTY
40
-
60
%
tRISE
-
tFALL
-
JTR
-
-
20
ns
-
20
ns
-
300
ps
(Note 4) SYNC
-2
-
2
µs
tmss
20
-
-
ns
tmdv
-
-
75
ns
tmsf
20
-
-
ns
Notes: 3. PLL bypass mode. The PLL generates a 32.768 MHz master clock when enabled.
4. Sampling synchronization between multiple CS5378 devices receiving identical SYNC signals.
DS639F1
16