CS5371A-ISZ(2006) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5371A-ISZ
(Rev.:2006)

Low-power, High-performance ∆Σ Modulators

Cirrus Logic 

CS5371A CS5372A

VA+

VA+

OUTR+

CS3301A OUTF+

CS3302A

AMPLIFIER OUTF-

OUTR-

VA-

680

680

20nF

680

C0G

680

VA-

VA+

10 Ω

VREF

2.5 V

100µF

VA-

VA+

VA+

OUTR+

CS3301A OUTF+

CS3302A

AMPLIFIER OUTF-

OUTR-

VA-

VA-

680

680

20nF

680

C0G

680

VA+

VD

0.1µF

0.01µF

VD

VA+

INR+

INF+

20nF

C0G

INF-

INR-

VD

MDATA1

MFLAG1

PWDN1

MCLK

MSYNC

0.01µF

VREF+

CS5372A

∆Σ Modulator

VREF-

OFST

INR-

INF-

20nF

C0G

INF+

INR+

VA-

MDATA2

MFLAG2

PWDN2

GND

VA-

0.1µF

VDD2

MDATA1

MFLAG1

GPIO

MCLK

MSYNC

CS5376A

Digital Filter

GPIO

MDATA2

MFLAG2

GPIO

GND

Figure 12. Digital Signals

5. DIGITAL SIGNALS

The CS5371A and CS5372A modulators are

designed to operate with the CS5376A digital

filter. The digital filter generates the modulator

clock and synchronization signals (MCLK and

MSYNC) while receiving back the modulator

one-bit ∆Σ conversion data and over-range

flag (MDATA and MFLAG).

5.1 MCLK Connection

The CS5376A digital filter generates the mas-

ter clock for CS5371A and CS5372A, typically

2.048 MHz, from a synchronous clock input

from the external system. If MCLK is disabled

during operation, the modulators will enter a

power down state after approximately 40 µS.

By default, MCLK is disabled at reset and is

enabled by writing the digital filter CONFIG

register.

MCLK must have low jitter to guarantee full an-

alog performance, requiring a crystal- or

VCXO-based system clock input to the digital

filter. Clock jitter on the digital filter CLK input

directly translates to jitter on MCLK.

5.2 MSYNC Connection

The CS5376A digital filter also provides a syn-

chronization signal to the CS5371A and

CS5372A modulators. The MSYNC signal is

automatically generated following a rising

edge received on the digital filter SYNC input.

By default, MSYNC generation is disabled at

reset and is enabled by writing the digital filter

CONFIG register.

The input SYNC signal to the CS5376A digital

filter sets a common reference time t0 for mea-

surement events, thereby synchronizing ana-

log sampling across a measurement network.

The timing accuracy of the received SYNC sig-

nal from measurement node to measurement

node must be ±1 MCLK to maximize the

DS748F1

19

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