
DIGITAL CHARACTERISTICS (CONT.)
SYNC
CS5371A CS5372A
MCLK
(2.048 MHz)
MSYNC
t0
MDATA
(512 kHz)
MFLAG
TDATA
(256 kHz)
Figure 6. System Timing Diagram
MCLK
(2.048 MHz)
MSYNC
MDATA
(512 kHz)
MFLAG
12
tmss
tmsh
t0
tmsync
tmclk
tmdata
Figure 7. MCLK / MSYNC Timing Detail
DS748F1