CS5320-KL1 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5320-KL1

24-Bit Variable Bandwidth A/D Converter Chipset

Cirrus Logic 

CS5320/21/22

CS5322 SWITCHING CHARACTERISTICS (continued)

Parameter

MCLK Frequency

MCLK Duty Cycle

Rise Times:

Any Digital Input

Any Digital Output

Fall Times:

Any Digital Input

Any Digital Output

SYNC Setup Time to CLKIN rising

SYNC Hold Time after CLKIN rising

CLKIN edge to MCLK edge

MCLK rising to Valid MDATA

MSYNC Delay from MCLK rising

Symbol

(Note 24)

fc

(Note 25)

trise

(Note 25)

tfall

(Note 26)

tss

tsh

tmss

tmsh

tmsd

Min

0.512

40

-

-

-

-

20

20

-

-

-

Typ

1.024

-

-

50

-

50

-

-

30

50

90

Max

1.1

60

100

200

100

200

-

-

-

-

-

Units

MHz

%

ns

ns

ns

ns

ns

ns

ns

ns

ns

Notes: 24. If MCLK is removed, the modulator will enter the power down mode.

25. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.

26. Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can return

low at any time as long as it remains high for at least one MCLK cycle.

CLKIN

t sh

t ss

SYNC

LSYNC*

MCLK

t mss

MSYNC

MDATA

t msd

t msd

t msh

VALID DATA

FILTER

SAMPLES

DATA

MFLG

* Internal timing signal generated in the CS5322

t msh

VALID DATA

Figure 17. CS5320/21/CS5322 Interface Timing

14

DS454PP1

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