CS5320-KL1 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5320-KL1

24-Bit Variable Bandwidth A/D Converter Chipset

Cirrus Logic 

CS5320/21/22

sheet. The clock must have less than 300 ps jitter to

maintain data sheet performance from the device.

The CS5320/21 is equipped with loss of clock de-

tection circuitry which will cause the CS5320/21 to

enter a powered-down state if the MCLK is re-

moved or reduced to a very low frequency. The

HBR pin on the CS5320/21 modifies the sampling

clock rate of the modulator. When HBR = 1, the

modulator sampling clock will be at MCLK/4; with

HBR = 0 the modulator sampling clock will be at

MCLK/8. The chip set will exhibit about 3 dB less

S/N performance when the HBR pin is changed

from a logic "1" to a logic "0" for the same output

word rate from the CS5322.

2.6 Low Power Mode

The CS5320/21 includes a low power operating

mode (LPWR =1). When operated with LPWR = 1,

the CS5320/21 modulator sampling clock must be

restricted to rates of 128 kHz or less. Operating in

low power mode with modulator sample rates

greater than 128 kHz will greatly degrade perfor-

mance.

2.7 Digital Interface and Data Format

The MCLK signal (normally 1.024 MHz) is divid-

ed by four, or by eight inside the CS5320/21 to gen-

erate the modulator oversampling clock. The HBR

pin determines whether the clock divider inside the

CS5320/21 divides by four (HBR =1) or by eight

(HBR = 0). The modulator outputs a ones density

bit stream from its MDATA and MDATA pins pro-

portional to the analog input signal, but at a bit rate

determined by the modulator over sampling clock.

For proper synchronization of the bitstream, the

CS5320/21 must be furnished with an MSYNC sig-

nal prior to data conversion. The MSYNC signal,

generated by the CS5322, resets the MCLK

counter-divider in the CS5320/21 to the correct

phase so that the bitstream can be properly sampled

by the CS5322 digital filter.

When operated with the CS5322 digital filter the

output codes from the CS5320/21/22 will range

from approximately decimal -5,242,880 to

+5,242,879 for an input to the CS5320/21 of ±4.5

V. Table 1 illustrates the output coding for various

input signal amplitudes. Note that with a signal in-

put defined as a full scale signal (4.5 V with

VREF+ = 4.5 V) the CS5320/22 and CS5321/22

chipsets does not output a full scale digital code of

8,388,607 but is scaled to a lower value to allow

some overrange capability. Input signals can ex-

ceed the defined full scale by up to 5% and still be

converted properly.

Modulator Input

Signal

> (+VREF + 5%)

≈ (+VREF + 5%)

+VREF

0V

-VREF

≈ - (+VREF +5%)

> - (+VREF +5%)

CS5322 Filter

Output Code

HEX

Decimal

Error Flag Possible

53FFFF(H) +5505023

4FFFFF(H) +5242879

000000(H)

0

B00000(H) -5242880

AC0000(H) -5505024

Error Flag Possible

Table 1. Output Coding for the CS5320/21 and

CS5322 Combination

DS454PP1

21

Share Link: