CS5181 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5181 Datasheet PDF : 24 Pages
| |||
CS5181
Figure 11 illustrates the system connection diagram
for the chip. For best performance, each of the
supply pins should be bypassed to the nearest
ground pin on the chip. The bypass capacitors
should be located as close to the chip as possible. If
the chip is surface mounted the bypass capacitors
should be on the same side of the circuit card as the
chip.
The CS5181 is a high speed component that re-
quires adherence to standard high-frequency print-
ed circuit board layout techniques to maintain
optimum performance. These include the use of
ground and power planes, using low noise power
supplies in conjunction with proper supply decou-
pling, minimizing circuit trace lengths, and physi-
cal separation of digital and analog components
and circuit traces.
It is preferred that any clock oscillator circuitry be
located on a ground plane separate from the digital
plane in order to ensure that digital noise does not
induce clock jitter.
For additional insight, see the CDB5181 evaluation
board for more details. Also refer to Application
Note AN18 which covers layout and design rules
for high resolution data converters.
1 AGND1
DGND1 22
+5 V
0.1 µF 28 VA1+
8 VA2+
CS5181
VD1+ 21 0.1 µF +3.3 V
VD2+ 12
0.1 µF
7 AGND2
18 AGND3
+
10 µF
0.1 µF
4 VREFOUT
5 VREFIN
3 VREF-
+
10 µF
2 VREF+
0.1 µF
+
1 µF
6 VREFCAP
0.1 µF
20 Ω
3.8 Vpp Fully
Differential ~
CMV = 2.375 V
20 Ω
2200 pF
26 AIN+
27 AIN-
DGND2 11 0.1 µF
PWDN 25
MODE 24
RESET 23
SYNC 10
MFLAG 9
Control
Logic
MCLK 20
MCLK 19
Clock
Source
FSO 17
SCLK 14
SCLK 13
SDO 16
SDO 15
Data
Interface
2200 pF
The 3.8 Vpp fully differential input span is set by the converter’s internal voltage reference at 2.375 V.
An input span of 4.0 Vpp fully differential would result if an external voltage reference of 2.5 V is used.
Figure 11. CS5181 System Connection Diagram
DS250PP1
13
Share Link: 