CS5181 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5181

∆Σ Modulator & 400 kHz to 625 kHz 16-Bit ADC

Cirrus Logic 

CS5181

Instability Indicator

The MFLAG signal is functional in both modes of

operation of the part and indicates when the modu-

lator has been overdriven into an unstable condi-

tion. In the modulator only mode (MODE = 0), the

MFLAG signal will remain set for 3 MCLK cycles

when the modulator goes unstable, before being re-

turned to the reset state. While the input condition

causing modulator instability persists, the MFLAG

signal will continually get set for 3 MCLK cycles

and then get reset.

When the decimation filter on the part is operation-

al (MODE = 1), the MFLAG signal is set when the

modulator goes unstable. In this mode, however,

the MFLAG signal stays set until 5,120 MCLK cy-

cles after the input condition causing modulator in-

stablility is removed. This delay is provided to

allow the digital filter time to settle, and the part

will output fully settled conversion words after the

MFLAG signal goes low.

Digital Filter Characteristics

Figure 9 illustrates the magnitude versus frequency

plot of the converter when operating at a 625 kHz

output word rate. The filter is a non-aliasing 4265

tap filter with a -3 dB corner at 0.4495 of the output

word rate and an out-of-band attenuation of at least

90 dB at frequencies above one half the output

word rate. The passband ripple is less than

±0.05 dB up to the -3 dB corner frequency.

Figure 10 illustrates the phase response of the dig-

ital filter with the converter operating at 625 kHz

output word rate. The filter characteristics change

proportional to changes in the MCLK rate.

The group delay of the digital filter is 2370 MCLK

cycles (59.3 µs with MCLK = 40 MHz), and the

settling time is 4740 MCLK cycles (118.5 µs).

Serial Interface

The CS5181 has a serial interface through which

conversion words are output in a synchronous self-

clocking format. The serial port consists of the Se-

Figure 9. CS5181 Digital Filter Magnitude Response

(MCLK = 40 MHz)

250.00

200.00

150.00

100.00

50.00

0.00

-50.00

-100.00

-150.00

-200.00

-250.00

0

50k

100k

150k

200k

250k

Freq (Hz)

300k

Figure 10. CS5181 Digital Filter Phase Response

(MCLK = 40 MHz)

rial Data Output pin (SDO), and its complement

(SDO); Serial Clock (SCLK), and its complement

(SCLK); and the Frame Sync Output (FSO). FSO

falls at the beginning of an output word. Data is

output in twos complement format, MSB first.

FSO stays low for 16 SCLK cycles. SCLK is out-

put at a rate equal to MCLK/3.

Power Supplies / Board Layout

The CS5181 requires an analog supply voltage of

5.0 Volts and a digital supply voltage of 3.3 Volts

(nominal) for proper operation.

12

DS250PP1

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