CS4525 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4525

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

CS4525

9. REGISTER DESCRIPTIONS

All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state.

9.1 Clock Configuration (Address 01h)

7

EnSysClk

6

DivSysClk

5

ClkFreq1

4

ClkFreq0

3

HP/MutePol

2

HP/Mute

1

PhaseShift

0

FreqShift

9.1.1

SYS_CLK Output Enable (EnSysClk)

Default = 1

Function:

This bit controls the output driver for the SYS_CLK signal. When cleared, the output driver is disabled and

the SYS_CLK pin is high-impedance. When set, the output driver is enabled.

If the SYS_CLK output is unused, this bit should be set to ‘0’b to disable the driver.

EnSysClk Setting

Output Driver State

0 ..........................................Output driver disabled.

1 ..........................................Output driver enabled.

9.1.2

SYS_CLK Output Divider (DivSysClk)

Default = 0

Function:

This bit determines the divider for the XTAL clock signal for generating the SYS_CLK signal.

This divider is only available if the clock source is an external crystal attached to XTI/XTO and the

SYS_CLK output is enabled.

DivSysClk Setting

SYS_CLK Output Frequency

0 .......................................... FSYS_CLK = FXTAL

1 .......................................... FSYS_CLK = FXTAL/2

9.1.3

Clock Frequency (ClkFreq[1:0])

Default = 01

Function:

These bits must be set to identify the nominal clock frequency of the crystal attached to the XTI/XTO pins

or that of the input SYS_CLK signal. See the XTI Switching Specifications table on page 23 and the

SYS_CLK Switching Specifications table on page 23 for complete input frequency range specifications.

ClkFreq[1:0] Setting

Specified Nominal Input Clock Frequency

00 ........................................18.432 MHz

01 ........................................24.576 MHz

10 ........................................27.000 MHz

11 ......................................... Reserved

DS726PP1

69

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