CS4226 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4226

Surround Sound Codec

Cirrus Logic 

CS4226

3.12 Auxiliary Port Mode Byte (0Fh)

B7

ACK1

B6

ACK0

B5

AMS1

B4

AMS0

B3

ASCK

B2

ADF2

B1

ADF1

This byte is not available when the receiver is functioning.

ADF2-ADF0

Data format

0 - Right justified, 20-bit data

1 - Right justified, 18-bit data

2 - Right justified, 16-bit data

3 - Left justified, 20-bit

4 - I2S compatible, 20-bit

5 - Not used

6 - Not used

7 - Not used

ASCK

Sets the polarity of clocking data

0 - Data clocked in on rising edge of SCLKAUX

1 - Data clocked in on falling edge of SCLKAUX

AMS1-AMS0

Sets the mode of the port.

0 - Slave

1 - Master Burst - SCLKAUXs are gated 128 fs clocks

2 - Master Non-Burst - SCLKAUXs are evenly distributed in LRCKAUX frame

3 - Not used - default to slave

ACK1-ACK0

Set number of bit clocks per Fs period.

0 - 128

1 - 48 - Master Burst or Slave mode only

2 - 32 - All input formats will default to 16 bits.

3 - 64

This register defaults to 00h.

B0

ADF0

DS188F4

29

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