CS4226 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4226 Datasheet PDF : 37 Pages
| |||
CS4226
3.9 Input Control Byte (0Ch)
B7
B6
B5
B4
B3
B2
B1
B0
OVRM
VM
BM
PM
GNR1
GNR0
GNL1
GNL0
OVRM
ADC Overflow Mask
0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold
1- No Masking
VM
Validity Error Mask
0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold
1- No Masking
BM
Biphase Error Mask
0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold
1- No Masking
PM
Parity Error Mask
0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold
1- No Masking
GNL1-GNL0
Sets left input gain
0 - 0 dB
1 - 3 dB
2 - 6 dB
3 - 9 dB
GNR1-GNR0
Sets right input gain
0 - 0 dB
1 - 3 dB
2 - 6 dB
3 - 9 dB
This register defaults to 00h.
3.10 ADC Status Report Byte (Read Only) (0Dh)
B7
LVM1
B6
LVM0
B5
LVR2
B4
LVR1
LVL2-LVL0, LVR2-0 Left and Right ADC output level
0 - Normal output levels
1 - -6 dB level
2 - -5 dB level
3 - -4 dB level
4 - -3 dB level
5 - -2 dB level
6 - -1 dB level
7 - Clipping
B3
LVR0
B2
LVL2
B1
LVL2
B0
LVL0
LVLM1-LVLM0
Mono ADC output level
0 - Normal output level
1 - -6 dB level
2 - -3 dB level
3 - Clipping
These bits are 'sticky'. They constantly monitor the ADC output for the peak levels and hold the max-
imum output. They are reset to 0 when read.
This register is read only.
DS188F4
27
Share Link: 