CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

5.8.1

System Control Register 1 — SYSCON1

23

1

15

SIREN

7

TC2S

22

21

Reserved

14

13

CDENRX

CDENTX

6

5

TC2M

TC1S

20

IRTXM

12

LCDEN

4

TC1M

19

WAKEDIS

11

DBGEN

3

18

17

16

EXCKEN

ADCKSEL

10

9

8

BZMOD

BZTOG

UART1EN

2

1

0

Keyboard Scan

The System Control register is a 21-bit read/write register that controls the general configuration of the

CL-PS7111 as well as modes for peripheral devices. All bits in this register are cleared by a system reset.

Bit Description

23 This bit must always be set to ‘1’.

22:21 Reserved

20 IRTXM: IrDA Tx mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means each ‘0’ bit transmitted

is represented as a pulse of width 3/16th of the bit rate period. Setting this bit means each ‘0’ bit is represented as a

pulse of width 3/16th of the period of 115,200 bit rate clock, that is, 1.6 µs, regardless of the selected bit rate. Setting

this bit reduces power consumption, but probably reduces transmission distances.

19 WAKEDIS: Setting this bit disables wake-up from standby mode through the WAKEUP + KBD inputs.

18 EXCKEN: External expansion clock enable. If this bit is set, the EXPCLK is enabled continuously; it is the same speed

and phase as the CPU clock, and free-run all the time the main oscillator is running. Do not leave this bit set for power

consumption reasons. If the system enters the standby state, the EXPCLK is undefined. If this bit is clear, EXPCLK is

active during memory cycles only to the expansion slots that have external wait-state generation enabled.

17:16 ADCKSEL: Microwire®/SPI® peripheral clock speed select. This 2-bit field selects the frequency of the ADC sample

clock, which is twice the frequency of the synchronous serial ADC interface clock. The following table shows the avail-

able frequencies, assuming operation at 18.432-MHz mode. The frequencies obtained at 13-MHz mode can be found

on Table 3-17 on page 41.

Bit

ADC Sample Frequency (kHz) ADC interface frequency (kHz) —

17 16

SMPCLK

ADCCLK

00

8

4

01

32

16

10

128

64

11

256

128

15 SIREN: HP SIR protocol encoding enable. If the UART is not enabled, this bit has no effect.

48

REGISTER DESCRIPTIONS

September 1997

PRELIMINARY DATA BOOK v2.0

Share Link: