CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

4. MEMORY MAP

The lower two Gbytes of the address space is allocated to ROM and expansion. The 0.5 Gbyte of address

space, 0xC000 0000–0xDFFF FFFF, is allocated to DRAM.The remaining Gbyte, minus 8K for the internal

registers, is not accessible in the CL-PS7111. Program the MMU of the CL-PS7111 to generate an abort

exception to access this area.

Internal peripherals addressed through a set of internal memory locations, 0x8000 0000–0x800 1FFF, are

the internal registers of the CL-PS7111.

Table 4-1 shows the mapping of the 4-Gbyte address range of the ARM710a microprocessor in the

CL-PS7111. Note that although 2 Kbytes of SRAM are available, the full address is decoded for the SRAM

segment starting at 0x6000 0000. The mapping in Table 4-1 assumes that two CL-PS6700 PC CArd con-

trollers are connected. If this functionality is not required, the NCS[4] and NCS[5] memory is available as

general SRAM/flash/ROM/expansion space. The Boot ROM is not fully decoded; the boot code repeats

within the 256-Mbyte space from 0x7000 0000–0x8000 0000. THe SRAM is fully decoded so no data is

written or read from locations more than 2 Kbytes above the base address.

Table 4-1. CL-PS7111 Memory Map

Address

F000.0000

E000.0000

D000.0000

C000.0000

8000.2000

8000.0000

7000.0000

6000.0000

5000.0000

4000.0000

3000.0000

2000.0000

1000.0000

0000.0000

Contents

Size

Unused

256 Mbytes

Unused

256 Mbytes

DRAM Bank 1

256 Mbytes

DRAM Bank 0

256 Mbytes

Unused

~1 Gbyte

Internal registers

8 Kbytes

Boot ROM

128 bytes

On-chip SRAM

2 Kbytes

PCMCIA-1 (NCS[5]) 4*64 Mbytes

PCMCIA-0 (NCS[4]) 4*64 Mbytes

Expansion (NCS[3]) 256 Mbytes

Expansion (NCS[2]) 256 Mbytes

ROM Bank 1 (NCS[1]) 256 Mbytes

ROM Bank 0 (NCS[0]) 256 Mbytes

September 1997

PRELIMINARY DATA BOOK v2.0

43

MEMORY MAP

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